1. Field of the Invention
The present invention concerns a method and a system for compensating the non-linearity of a sigma-delta analog-to-digital converter.
2. Description of the Related Art
Equipment in all fields, electronic or otherwise, consumer or professional, increasingly employs digital rather than analog processing. This choice is often justified by technical advantages that are now well known, such as very stable parameters, excellent reproducibility of results, and increased functionality.
The external world being inherently analog, in most cases analog-to-digital converters (ADC) and digital-to-analog converters (DAC) provide at some level the interface between the external world and the digital core of the equipment.
The development of powerful digital processors has created a need for a high-resolution analog-to-digital converter compatible with CMOS VLSI (Very Large Scale Integration) technologies. The sigma-delta modulation converter in particular has exploited technological developments.
As shown in FIG. 1, a sigma-delta analog-to-digital converter primarily includes an adder 1, a noise-shaping filter 4, a quantizer 5, a digital filter 6 and a feedback loop 8 connecting the output of the quantizer 5 to the negative input 3 of the adder 1. The feedback loop 8 includes an analog-to-digital converter 7. A sample-and-hold device (not shown), usually on the input side of the adder 1, oversamples the signal at a given frequency and then maintains the level at the output 2 constant to enable the sigma-delta analog-to-digital converter to process the data. The noise-shaping filter 4 shapes the noise spectrum to attenuate the noise power in the frequency range of the wanted signal. The quantizer 5 employs a set of discrete levels and associates the closest discrete level with the analog value at its input. This introduces an error known as xe2x80x9cquantizing noisexe2x80x9d. The performance of a converter is conditioned by the quantizing noise power. To this end, the oversampling performed in the sample-and-hold device (not shown) and the feedback loop 8 xe2x80x9cpushesxe2x80x9d the maximum quantizing noise power out of the pass-band of the signal (the band of frequencies at which the system operates). The digital filter 6 at the output of the sigma-delta analog-to-digital converter, also known as a decimation filter, eliminates the shaped quantizing noise and undersamples the output signal. The digital-to-analog converter 7 has a transfer function that links the input (quantizing) digital levels delivered by the quantizer 5 to output analog values that are then fed to the negative input 3 of the adder 1. The analog-to-digital converter 7 associates a corresponding analog output value with each quantizing input level.
The fundamental principle of the sigma-delta analog-to-digital converter consists firstly of oversampling the signal using the analog sample-and-hold device, pushing the quantizing noise power maximum outside the pass-band of the signal, by integrating the quantizer into a feedback loop, and then filtering the signal obtained by means of a digital filter 6. These conjugate actions initially xe2x80x9cdilutexe2x80x9d the quantizing noise in a wide band thanks to the oversampling, shape the noise spectrum, and then filter the quantizing noise to retain only the wanted band of the signal.
Using a multibit quantizer associated with a multibit digital-to-analog converter in the feedback loop of a sigma-delta analog-to-digital converter is beneficial because it improves the signal/noise ratio and dynamic range of the sigma-delta analog-to-digital converter.
However, the performance of the sigma-delta analog-to-digital converter is highly dependent on the linearity of the sigma-delta analog-to-digital converter 7 used in the feedback loop 8.
One prior art solution that has been proposed for calibrating the multibit digital-to-analog converter regardless of the number of levels is described by SARHANG-NEJAD and G. C. TEMES, xe2x80x9cA High Resolution Multibit Sigma Delta ADC with Digital Correction and Relaxed Amplifier Requirementsxe2x80x9d, IEEE Journal of solid state circuits, vol. 28, N 6, June 1993, pages 648-660. It proposes to improve the performance of the sigma-delta analog-to-digital converter by measuring the non-linearities of the digital-to-analog converter 7 during a calibration phase. During the calibration phase, the multibit sigma-delta analog-to-digital converter is converted into a one-bit sigma-delta analog-to-digital converter (only the most significant bit at the output of the quantizer is considered). The calibration phase essentially employs the components shown in FIG. 2, which shows the adder 1, the noise-shaping filter 4, the quantizer 5 and the decimation filter 6. The digital-to-analog converter 7 is replaced by switching means Ea for imposing at the negative input 3 of the adder 1 either a positive voltage Vref or a negative voltage xe2x88x92Vref, depending on the value of the output of the one-bit quantizer 5. The digital-to-analog converter 7 is then placed at the positive input 2 of the adder 1. A counter Eb controls the digital-to-analog converter 7 by feeding it a digital signal (corresponding to one of the levels available to the quantizer 5) so that it generates an analog signal at the input of the one-bit sigma-delta analog-to-digital converter. An adder Ec receiving the output signal of the counter Eb and the output signal of the decimation filter 6 calculates a correction value that is stored in a memory module Ed. The counter Eb also controls addressing of the memory module Ed.
Each correction value represents a digital error caused by the digital-to-analog converter 7 in converting between a digital value and its analog conversion. During the phase of normal use, the sigma-delta analog-to-digital converter is equivalent to that shown in FIG. 1 with a digital correction module (not shown) containing the correction values added in front of the decimation filter 6. All digital values leaving the quantizer 5 are corrected by the digital correction module before reaching the decimation filter 6. Thus the corrected digital value entering the decimation filter 6 is substantially equal to the analog value at the negative input 3 of the adder 1.
The above technique has a number of drawbacks, associated with the manner in which the correction values are measured. In the calibration phase (FIG. 2), the output of the digital-to-analog converter 7 is fed to the positive input 2 of the adder 1, whereas under normal operating conditions (FIG. 1 plus correction module) the digital-to-analog converter 7 is in the feedback loop 8 and its output is fed to the negative input 3 of the adder 1. The behavior of the digital-to-analog converter 7 differs between the calibration phase and normal operating conditions because the two inputs of the adder 1 are different. The two inputs of the adder 1 do not have exactly the same capacitance, because it generally uses switched capacitors.
FIG. 3 shows an adder using switched capacitors. The switches 9, 10 and 12, 13 respectively switch a capacitor C1 and a capacitor C2 which are connected to a ground 14. The adder has two inputs E1 and E2 respectively connected to the capacitors C1 and C2. An operational amplifier 11 performs the addition operation by means of a feedback capacitor C. The capacitors C1 and C2 theoretically have the same capacitance. However, in practice, because of manufacturing tolerances, their capacitances are different and the gain between the two inputs is therefore different.
During the calibration phase, the digital-to-analog converter is therefore connected to the input E1 and the values injected are measured accurately. During the normal operation phase, the digital-to-analog converter included in the feedback loop is connected to the input E2 of the adder. Because the capacitors C1 and C2 are in practice different, the values measured during the calibration phase are therefore not in fact the values injected during the normal operation phase. Also, the accuracy of the measurement may be influenced by offset voltages inherent to the sigma-delta analog-to-digital converter. The offset voltages may not be a problem during the normal operation phase, but can become a problem during the calibration phase because it entails measuring DC voltages.
The invention aims to solve the above problem by retaining the structure of the sigma-delta analog-to-digital converter during the calibration phase and using only digital signals.
The invention proposes a method of compensating the non-linearity of a sigma-delta analog-to-digital converter with N quantizing levels and including a digital-to-analog converter in a feedback loop. N is an integer greater than two. The method includes a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values Ci, where i is a positive integer from 1 to N, calculated during a calibration phase. According to a general feature of the invention, the correction values Ci are calculated from values of the output of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels, for example modifiable levels. The number N is a positive integer greater than 2.
The correction values Ci are used to correct errors caused by the digital-to-analog converter. The corrections are preferably made instantaneously during the normal operation phase.
The method in accordance with the invention of compensating non-linearity includes a calibration phase during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels Xm, XM and Xi, where i is from 1 to Nxe2x88x922; during a period P1i, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the sigma-delta analog-to-digital converter are processed digitally; this calibration phase is executed Nxe2x88x922 times, retaining the levels Xm and XM, and taking successively for the level Xi the Nxe2x88x922 levels other than the levels Xm and XM. The correction values Ci of the Nxe2x88x922 levels other than Xm and XM are advantageously calculated using the processed values, the Nxe2x88x922 correction values Ci being adapted to modify the Nxe2x88x922 levels other than Xm and XM during the normal operation phase.
The levels Xm, XM and Xi are digital values that are converted into analog values in accordance with a transfer function of the digital-to-analog converter.
The method can further include, during the calibration phase and before calculating the correction values Ci, at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels Xm and XM. During a period P2, said predetermined value is delivered to the input of the sigma-delta analog-to-digital converter, and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally. In other words, step F advantageously eliminates any offset voltages in the sigma-delta analog-to-digital converter.
For example, if step F is performed only once, the periods P1i can all be equal to one another and equal to the period P2.
The calibration phase presupposes that Xi is different from Xm and XM.
In accordance with the invention the sigma-delta analog-to-digital converter with N quantizing levels is converted into a sigma-delta analog-to-digital converter with a number of quantizing levels less than N by modifying quantizing threshold values and by digital processing using internal comparators. In the general case the sigma-delta analog-to-digital converter with N quantizing levels is converted into a sigma-delta analog-to-digital converter with three quantizing levels, and if the optional step F (offset voltage correction) is implemented, it is also converted into a sigma-delta analog-to-digital converter with two quantizing levels.
According to one advantageous feature of the invention, the levels Xm and XM are respectively the minimum value and the maximum value of the N quantizing levels.
In one embodiment of the invention, during the normal operation phase, its correction value Ci is added to each level Xi present at the output of the quantizer. Thus the digital value after correction is substantially equal to the analog value at the output of the digital-to-analog converter.
In one advantageous variant of the invention, said predetermined value is equal to zero and, during the calibration phase, and during the period P1i for each level Xi, the number Ni of values equal to XI and the total number NTi of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S1i of the NTi values is calculated. The periods P1i, which are not all equal a priori, can depend on each intermediate level Xi. In this case, step F of the calibration phase is executed Nxe2x88x922 times, each time taking a period P2i equal to each period P1i, and a sum S2i is calculated of all the values leaving the sigma-delta analog-to-digital converter during each execution, after which a correction value Ci corresponding to the value Xi is calculated from the equation (for i from 1 to Nxe2x88x922):       C    i    =                    S2        i            -              S1        i                    N      i      
The period P1i for each level Xi is preferably equal to the period needed to count the number Ni of values equal to Xi at the output of the sigma-delta analog-to-digital converter (A2) until the number Ni is equal to a given number N0.
If step F is executed only once (in which case all the periods P1i are equal to each other and to P2), there is only one sum S2 and Ci can be calculated from the following equation (for i from 1 to Nxe2x88x922):       C    i    =            S2      -              S1        i                    N      i      
There are various ways to calculate the correction values Ci.
The invention also proposes a system for compensating the non-linearity of a sigma-delta analog-to-digital converter with N quantizing levels including a digital-to-analog converter and a digital filter. According to a general feature of the invention, the system includes means for implementing the various phases previously described.
In a preferred embodiment, the calculating and modifying means include:
counter means for counting the values leaving the sigma-delta analog-to-digital converter,
at least one accumulator for summing the values leaving the sigma-delta analog-to-digital converter,
storage means for memorizing numbers delivered by the counting means and the accumulator,
processor means for performing calculations on the memorized numbers and generating control signals in the system for controlling the various phases,
a correction module between the quantizer and the digital filter and communicating with the processor means, and
comparators and a digital processor module internal to the N-level quantizer and capable of converting the quantizer into a quantizer with fewer than N quantizing levels.